The present invention relates to a phase-change memory and, in particular, to a readout circuit for use in the phase-change memory.
A semiconductor memory includes a volatile memory which loses memory information when power supply is turned off and a nonvolatile memory which retains memory information even when power supply is turned off. For example, the volatile memory is a Dynamic Random Access Memory (DRAM) or a Static Random Access Memory (SRAM), while the nonvolatile memory is an Electrically Erasable Programmable Read Only Memory (EEPROM) or a flash memory. In a recent mobile information terminal, for the purpose of miniaturization and power saving, the flash memory which retains memory information even when power supply is turned off is commonly used.
However, higher performance and/or higher functionality is desired as a recent mobile memory. As a mobile memory, in addition to large capacity, fast access such as a Double Data Rate (DDR) system, multiple bits of a data bit width, and low power consumption for ensuring battery life are required. Thus, a phase-change memory using a phase-change material comes to the front, and its development proceeds. The phase-change memory is a nonvolatile memory using two different phase states of the phase-change material as memory information. A chalcogenide material (such as Ge, Sb and Te) is used as the phase-change material.
FIG. 1 shows a memory cell of a phase-change memory. The memory cell is constituted from a phase-change element GST made of a chalcogenide material (such as Ge, Sb and Te), and a selection transistor C1 for selecting a memory cell. One terminal of the phase-change element GST is connected to a bit line BL of the memory cell, while the other terminal thereof is connected to a drain of the selection transistor C1. A source of the selection transistor C1 is connected to GND, while a gate thereof is connected to a Row selection signal VG. The selection transistor conducts an electric current therethrough in response to the Row selection signal VG, whereby a writing/reading operation is carried out via the bit line BL.
The phase-change element GST uses a property that a chalcogenide material (such as Ge, Sb and Te) becomes either an amorphous state (high resistance) or a crystal state (low resistance) by applying heat thereto. By controlling applied voltage and applied time, the chalcogenide material is changed between a high resistance (reset) state and a low resistance (set) state by means of Joule heat generated by a current. The state where the phase-change element GST becomes a amorphous state to present high resistance is referred to as a “reset state”, while the state where the phase-change element GST becomes a crystal state to present low resistance is referred to as a “set state”. The phase-change element GST made of a chalcogenide material becomes low resistance at the crystal state, while it becomes high resistance at the amorphous state. The phase-change element GST is a memory element that uses a state difference as memory information. This phenomenon was discovered by Stanford Ovshinsky. Now, the phase-change element by the designation of Ovonic Unified Memory (OUM) and the like gets a lot of attention as a memory material with potential for a universal memory.
Writing into a phase-change element GST requires applying a large current thereto because a phase state of the phase-change element GST is to be changed. Generally, writing current published in a VSLI symposium and/or an ISSCC, in particular, a current at a reset program (changed from a crystal state to an amorphous state) is reported to be in the range of 400 μA to 600 μA. However, in order to satisfy low consumption current required for the mobile memory, it is necessary to reduce this program current. In the ISSCC2006 (P. 140, 7.5 A, 0.1 μm, 1.8V, 256 Mb, and 66 MHz Synchronous Burst PRAM), a method of reducing a consumption current by reducing a bit width simultaneously programmed has been proposed as a method of reducing a program current in a product specification.
A mobile memory is required to reduce a reset program current to the range of about 100 μA to 200 μA. Thus, the search for a composition or material for a phase-change element GST is proceeding. It is also required that access time achieves fast access like a DRAM, and internal access speed thereof is desired to be in the range of about 10 ns to 20 ns. FIG. 2 shows a relationship diagram between a reset program current Ireset and values of a set resistance Rset and a reset resistance Rrst at a set state and a reset state. As shown in FIG. 2, the value of each of the resistances Rset and Rrst of the phase-change element GST considerably changes in the range of one or two order or more as the program current value changes. A phenomenon is seen which reset and set resistance values increase when a reset program current (Ireset) is reduced.
As will be described later, a set program current (Iset) is less than a reset program current (Ireset), and the maximum voltage and the maximum current at the programming are restricted. For example, a set program current Iset in FIG. 2 is set to about 60% of the current value of the reset program current Ireset. For example, in the case of the reset program current of 200 μA, the reset resistance is about 10 MΩ, and the set resistance is about 100 KΩ. In the case of the set resistance of 100 KΩ, the set readout current becomes lower to about 4 μA. Thus, there has been a problem that it is difficult to achieve fast readout because the set readout current becomes smaller.
Hereinafter, these problems will be described more in detail. FIG. 3 shows a circuit diagram of a sense amplifier and a column selecting switch (hereinafter, referred to as a “Y switch”) as a conventional readout circuit. FIG. 4 shows a relationship diagram between a program resistance value and voltage V in the phase-change element GST. FIG. 5 shows a relationship diagram between a program resistance value and a current I in the phase-change element GST. FIG. 6 shows profiles of current and temperature at programming of a phase-change memory. FIG. 7 and FIG. 8 respectively show volt-ampere characteristic diagrams at an amorphous state (reset state) and a crystal state (set state) of the phase-change element GST.
In FIG. 6 which shows profiles of current and temperature at programming of a general phase-change memory, program time is shown in the horizontal axis, while current and temperature profiles are shown in the longitudinal axis. Since the temperature profile here is determined by the supplied current, it is simplified and shown as the same as the current profile. In the case where the phase-change element GST is changed to an amorphous state, a large reset program current Ireset is supplied for a short time. The phase-change element GST is caused to generate heat due to the reset program current until the temperature exceeds melted temperature (Tm), and the phase-change element GST is then cooled rapidly. Rapid cooling causes the phase-change element GST to become an amorphous state.
Further, in the case where the phase-change element GST is changed from the amorphous state to a crystal state, a set program current Iset smaller than the reset program current Ireset is supplied to the phase-change element GST for a time longer than that at the reset program. The phase-change element GST is caused to generate heat for a long time at temperature lower than the melted temperature (Tm). Slow cooling from low temperature causes the phase-change element GST to become a crystal state. Generation of heat when to change the phase states is caused by a current flowing to a phase-change element material itself or resistance (R) such as a heater material. The product of a square value of the flowing current (I) and the resistance (R) is a calorific value.
In FIG. 7 which shows a device property of the phase-change element GST at a reset state, applied voltage is shown in the horizontal axis, while a current is shown in the longitudinal axis. The applied voltage VGST to the reset resistance Rrst in the phase-change element GST at a reset state is gradually raised. When the applied voltage reaches predetermined constant voltage Vth, the slope in FIG. 7 changes largely, and a phenomenon in which the current according to dynamic resistance Rdyn flows rapidly occurs. This phenomenon is called as Ovonic Threshold Switching (OTS). This voltage Vth is called as transition voltage. When the current more than the minimum reset program current Ireset(min) is applied after occurrence of OTS, the phase-change element GST is changed to a reset state.
Further, when a current less than the maximum set program current Isafe but more than the minimum set program current Iset(min) is applied thereto, the phase-change element GST is allowed to change to a set state. The difference between the minimum reset program current Ireset(min) and the maximum set program current Isafe is a margin of the program current for programming the phase-change element GST to either the reset state or the set state. The voltage VGST when obtaining the maximum set program current Isafe is defined as maximum set program voltage Vsafe. Moreover, the transition voltage Vth at which OTS occurs varies depending on temperature dependency and/or a condition of a phase-change film. The maximum and minimum values of the transition voltage Vth are respectively defined as Vth(Max) and Vth(Min).
In FIG. 8 which shows a device property of the phase-change element GST at a set state, applied voltage is shown in the horizontal axis, while a current is shown in the longitudinal axis. Set resistance Rset is first indicated with respect to the applied voltage VGST. When the applied voltage VGST becomes predetermined voltage VH or more, it is under dynamic resistance Rdyn. The voltage VH at which the resistance property is changed is called as hold voltage VH. In the programming from a set state to a reset state, by applying the maximum set program voltage Vsafe or more thereto to supply the current of the minimum reset program current Ireset(min) or more thereto, the phase-change element GST is allowed to phase-change to a reset state.
Next, readout voltage Vread and readout current Iread at a reset state and a set state of the phase-change element will be described. At the reset state shown in FIG. 7, the readout voltage Vread has first to be set to the transition voltage Vth(min) or less. This is because of reasons as follows. In the case where voltage over the transition voltage Vth(min) is applied to a bit line BL, OTS occurs in the phase-change element to become a region of the dynamic resistance Rdyn. A current larger than the reset readout current Iread that flows when the phase-change element has high resistance thus flows. For that reason, it is mistakenly determined that the set readout current at low resistance state flows, whereby it is impossible to read out normally.
The readout current Iread has also to be the minimum set program current Iset(min) or less. This is because of reasons as follows. In the case where the applied voltage becomes the transition voltage Vth(min) or more even instantaneously when the readout voltage is applied to the bit line BL, the phase-change element GST becomes the dynamic resistance Rdyn region, whereby the current of the minimum set program current Iset(min) or more flows thereto. In this case, a phase change occurs in the phase-change element GST that is written to a reset state even though the readout is carried out, whereby the phase-change element GST may be rewritten to a set state. Mistakenly writing at the readout in this manner is referred to as “read disturb”.
Similarly, in the case of the set state in FIG. 8, similar conditions are also required. The readout voltage Vread has to be the maximum set program voltage Vsafe or less. In addition, in the case where the readout current Iread is the maximum set program current Isafe or less, the phase-change element GST leads to a reset state. This results in a permissible range. Ranges of readout voltage and a current for satisfying both conditions at the reset state and the set state are as follows.Vread<Vth(Min)<VH(<Vsafe)  Formula (1)Iread<Iset (<Isafe)  Formula (2)Thus, the ranges of the readout voltage and the current are required to be set so as to satisfy the conditions of the formulas (1) and (2) at the programming and readout for the phase-change element. These setups allow the phase-change element GST to function as a nonvolatile memory without erasing the written data at the readout.
In FIG. 3, a circuit diagram of a sense amplifier 201 and a Y switch 203 is shown as a conventional readout circuit. In a Magnetic Random Access Memory (MRAM) or a Resistance Random Access Memory (RRAM) end a memory element of a resistance program system such as a phase-change memory, a current sense amplifier type of sense amplifier is normally utilized. The current sense amplifier is a sense amplifier that reads out and detects a current flowing to a resistance element to amplify it. The sense amplifier 201 is set up so as to ensure the readout voltage and the current according to the formulas (1) and (2).
A bias circuit (including a comparator circuit 101 and a PMOS transistor P2) for controlling voltage and a current on the bit line BL in the memory cell is incorporated in the sense amplifier 201. The sense amplifier 201 is constituted from PMOS transistors P1, P2, a NMOS transistor N1 and a comparator circuit 101. The Y switch 203 is constituted from a plurality of NMOS transistors N3, N4. The sense amplifier 201 is connected to the Y switch 203 at the connection node Vbit so as to be connected to the bit line BL of the memory cell via the Y switch 203. In the following circuit diagrams, a NMOS transistor is represented by a transistor Nxx, while a PMOS transistor is represented by a transistor Pxx.
Drain, source and gate of the transistor P1 are respectively connected to a source of the transistor P2, a power supply Vdd, and a standby signal STB. Drain, source and gate of the transistor P2 are respectively connected to a sense amplifier output Vsa, the drain of the transistor P1, and reference voltage Vref. Drain, source and gate of the transistor N1 are respectively connected to the sense amplifier output Vsa, the connection node Vbit, and an output from the comparator circuit 101. A drain of each transistor in the Y switch 203 is connected to the connection node Vbit. Gates of the transistors in the Y switch 203 are respectively connected to Y selection signals (Y0, . . . and Yn). Sources thereof are respectively connected to the bit lines BL of the memory cells.
The connection node Vbit and the clamp voltage Vclmp are inputted to the comparator circuit 101, and the comparator circuit 101 outputs a comparison result to the gate of the transistor N1. A conductive state of the transistor N1 is controlled on the basis of the output from the comparator circuit 101 so that voltage of the connection node Vbit becomes equal to the clamp voltage Vclmp. By setting the clamp voltage Vclmp to voltage according to the formula (1), it is possible to hold the connection node Vbit to optimal constant voltage (clamp voltage Vclmp). Since the voltage applied to the memory cell is the same as the voltage at the connection node Vbit, the clamp voltage Vclmp is applied as the readout voltage.
Further, the maximum flowing current is set to the minimum set program current Iset(min) or less depending on the reference voltage Vref, which is a gate input of the transistor P2. The current flowing to the transistor P2 is the same as the current flowing to the transistor N1 and the readout current Iread of the memory cell. The readout current Iread becomes the minimum set program current Iset(min) or less, whereby it is possible to satisfy the formula (2).
During readout of the memory cell, the readout current Iread flows in accordance with memory information of the memory cell selected by the Y selection signal. The difference between the readout current Iread at a set state and a reset state causes output voltage of the sense amplifier output Vsa to be differentiated. The memory information in the memory cell is outputted as the sense amplifier output Vsa. Moreover, a comparator circuit (not shown in the drawings) compares and determines the sense amplifier output Vsa with the reference amplifier output to output a comparison result to an external interface circuit as memory cell data.
Next, the specific operation will be described with reference to current-voltage characteristics of the phase-change element. Here, it is assumed that transition voltage Vth(min) of the phase-change element is 0.5V and the minimum set program current Iset(min) is 50 μA. In this case, in view of a margin of the readout operation, the readout voltage Vread can be set to 0.4V, and set readout current Iread can be set to 40 μA. In order to achieve a fast readout operation, it is required to ensure the set readout current of a predetermined level or more. In order to ensure the set readout current Iread to 40 μA, it is desired that the set resistance value is 10 KΩ or less. Further, in view of production tolerance or the like, it is desired that the reset resistance value at a reset state has a margin in the range of one or two order with respect to the set resistance. It is desired that the reset resistance value is 1,000 KΩ or more.
It is necessary that a device property of the phase-change element GST is set so that the readout voltage Vread is 0.4V and the set readout current Iread is 40 μA. As shown in FIG. 4, even when the program resistance is 10 MΩ, the voltage VGST is held at 0.4V. Namely, even though the reset resistance increases up to about 10 MΩ, it is possible to keep the voltage VGST applied to the phase-change element GST at 0.4V or less. No OTS thus occurs.
Moreover, as shown in FIG. 5, the device property of the phase-change element GST is set so that the set readout current of 40 μA flows when the program resistance is 10 KΩ. When the resistance further increases up to 100 KΩ, the set readout current Iread becomes about 4 μA. Further, in the case where the resistance becomes too lower so that the resistance value is 1 KΩ, a current of 40 μA or more does not flow because current control is carried out at the transistor P2 in the sense amplifier. In FIG. 4 and FIG. 5, the voltage and current are controlled in accordance with the Ohm's law.
In this case, the program resistance satisfying that the readout voltage Vread is 0.4V and the set readout current Iread is 40 μA becomes 10 KΩ for the set resistance and 1,000 KΩ for the reset resistance. By carrying out the setting in this manner to constantly keen the current and voltage to be supplied to the phase-change element GST, it is possible to realize a nonvolatile memory and to achieve fast readout.
However, according to FIG. 2, the reset program current Ireset required to obtain the resistance value is about 800 μA, and the set program current Iset thereof thus becomes 480 μA (obtained by multiplying 800 by 60%). In the mobile memory required to reduce power consumption, the reset program current Ireset of 200 μA or less is required. In the case where the reset program current Ireset is 200 μA, the set resistance is 100 KΩ and the set resistance is 10,000 KΩ. The set readout current when the set resistance is 100 KΩ becomes 4 μA, and a fast readout operation is thus hardly carried out. In the case where the program current is made smaller in the phase-change memory in this manner, the set resistance value becomes larger. Therefore, there has been a problem that it is difficult to carry out fast readout because the readout current at a set state becomes smaller.
There are following patent documents as prior patent documents regarding a variable resistance value type of memory device. A memory cell disclosed in Japanese Unexamined Patent Application Publication No. 2005-71500 includes two selection transistors in parallel. One selection transistor conducts an electric current therethrough at readout, while two selection transistors conduct an electric current therethrough at writing, whereby the current flowing to the phase-change element is controlled. In Japanese Unexamined Patent Application Publication No. 2005-50424, writing conditions in which a writing voltage level and drop speed are differentiated in accordance with a verifying result of writing data are utilized. However, the above-mentioned patent documents are documents relating to a technique to program precisely, and they fail to disclose the problems in the case where the reset program current is made smaller according to the present invention.